Device scaling in advanced semiconductor nodes such as the 10 nm node and beyond has driven the contacted poly pitch (CPP) (i.e., the minimum center-to-center space between gates of adjacent transistors) to less than about 100 nm. Contacts to the source or drain of such transistors must fit within the space between the adjacent gates without shorting either gate to the source or drain. To achieve this, methods such as double or triple-patterning of source/drain contacts have been utilized. However, such multiple-patterning techniques require additional masks and manufacturing overhead. The use of additional masks can also degrade overlay (OVL) control between these contacts, the source or drain of the transistor to which the contact aligns, and adjacent features such as the gate of the transistor from which the contact must remain electrically-isolated to insure yield. Other techniques such as self-aligned contact (SAC) formation can reduce OVL degradation associated with multiple-patterning techniques, but require additional layers in the transistor device stack for proper contact formation.